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AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Pin Description (continued)
PIN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NAME
CSN2
CSP2
V CC
NBSKP
DH2
LX2
BST2
V DD2
DL2
GND2
GND1
DL1
V DD1
BST1
LX1
DH1
VRHOT
FUNCTION
Negative Current-Sense Input for SMPS2. Connect to the negative side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
Positive Current-Sense Input for SMPS2. Connect to the positive side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
Connect CSP2 to V CC to disable SMPS2. This allows the MAX17009 to operate as a 1-phase regulator.
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum. A V CC
UVLO event that occurs while the IC is functioning is latched, and can only be cleared by cycling V CC
power or by toggling SHDN .
North Bridge Skip Push-Pull Control Output. When NBSKP is high, the NB switching regulator is set to
forced-PWM mode. When NBSKP is low, the NB switching regulator is set to pulse-skipping mode. The
NBSKP level is set through the serial interface during normal operation.
NBSKP is high in shutdown and during soft-shutdown.
NBSKP is high in startup until commanded otherwise.
SMPS2 High-Side, Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also
used as an input to phase 2’s zero-crossing comparator.
Boost Flying-Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between V DD2
and BST2 charges the flying capacitor during the time the low-side FET is on.
Supply Voltage Input for the DL2 Driver. V DD2 is also the supply voltage used to internally recharge the
BST2 flying capacitor during the off-time of phase 2. Connect V DD2 to the 4.5V to 5.5V system supply
voltage. Bypass V DD2 to GND with a 1μF or greater ceramic capacitor.
SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to V DD2 . DL2 is forced low in shutdown.
DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip mode after
an inductor current zero crossing (GND2 - LX2) is detected.
Power Ground for SMPS2. Ground connection for the DL2 driver. Also used as an input to SMPS2’s zero-
crossing comparator. GND1 and GND2 are internally connected.
Power Ground for SMPS1. Ground connection for the DL1 driver. Also used as an input to SMPS1’s zero-
crossing comparator. GND1 and GND2 are internally connected.
SMPS1 Low-Side, Gate-Driver Output. DL1 swings from GND1 to V DD1 . DL1 is forced low in shutdown.
DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip mode after
an inductor current zero crossing (GND1 - LX1) is detected.
Supply Voltage Input for the DL1 Driver. V DD1 is also the supply voltage used to internally recharge the
BST1 flying capacitor during the off-time of phase 1. Connect V DD1 to the 4.5V to 5.5V system supply
voltage. Bypass V DD1 to GND with a 1μF or greater ceramic capacitor.
Boost Flying-Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between V DD1
and BST1 charges the flying capacitor during the time the low-side FET is on.
SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also
used as an input to phase 1’s zero-crossing comparator.
SMPS1 High-Side, Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below
1.5V (30% of V CC ). VRHOT is high impedance in shutdown.
______________________________________________________________________________________
17
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